1. Field of the Invention
The present invention generally relates to semiconductor device manufacturing, and more particularly to an improved technique for etching self-aligned via holes and wiring paths into a dielectric layer wherein the via holes self-align to the wiring paths.
2. Background of Invention
Semiconductor device manufacturing generally includes various steps including a patterning process. For example, the manufacturing of a semiconductor chip may start with, for example, CAD (computer aided design) generated device patterns and may continue with the effort to replicate these device patterns in a substrate in which semiconductor devices can be formed. The replication process may involve the use of a photolithography process in which a layer of photo-resist material may be first applied on top of a substrate, and then be selectively exposed according to a pre-determined device pattern. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to a certain solution. Next, the photo-resist may be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern. The photo-resist pattern may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.